1. Field of the Invention
The present invention relates to a flip chip type semiconductor device wherein semiconductor chips are mounted on a multilayer wiring substrate and a method for manufacturing the same. Particularly, the present invention relates to a flip chip type semiconductor device which can be manufactured at low cost and set the wiring pattern pitch of the multilayer wiring substrate at 10 xcexcm or less and a manufacturing method thereof.
2. Description of the Related Art
FIGS. 1A and 1B show a conventional flip chip type semiconductor device 101. In the flip chip type semiconductor device shown in FIG. 1A, external terminals (not shown) are formed in the peripheral sections of a semiconductor chip 102 or an active region on the semiconductor chip 102 in an area array arrangement. Protruding bumps 103 are formed out of a metal material such as a solder, Au, an Snxe2x80x94Ag alloy or the like on the external terminals, respectively.
This flip chip type semiconductor device 101 is mounted on a multilayer wiring mounted substrate 104 as shown in FIG. 1B. Electrode pads are formed on the multilayer wiring mounted substrate 104 to have the same pattern as the bump array pattern of the flip chip type semiconductor device 101. An end user mounts the flip chip type semiconductor device 101 on the multilayer wiring mounted substrate 104 while the bumps 103 of the device 101 aligned to the electrode pads of the multilayer wiring mounted substrate 104, respectively. If a solder is used as a bump material, the flip chip type semiconductor device 101 is mounted on the multilayer wiring mounted substrate 104 by an IR reflow step using flux.
However, the conventional flip chip type semiconductor device 101 has a disadvantage in that after mounting the semiconductor device 101 on the multilayer wiring mounted substrate 104, a temperature cycle characteristic, in particular, among mounting reliability factors deteriorates due to mismatch in the linear expansion coefficient between the multilayer wiring mounted substrate 104 and the flip chip type semiconductor device 101. To solve this disadvantage, the following measures have been conventionally taken.
First, with a view to making the linear expansion coefficient of the multilayer wiring mounted substrate 104 closer to that of silicon, a ceramic material such as AlN, mullite or glass ceramic, which is expensive as a material, has been used to minimize mismatch in the linear expansion coefficient, to thereby enhance mounting reliability. Although this attempt was effective for enhancing mounting reliability, it is applicable only to high-end super computers, large computers or the like because an expensive ceramic material is used for the multilayer wiring substrate.
In recent years, there is proposed a technique capable of enhancing mounting reliability by mounting a flip chip semiconductor device while arranging an under-fill resin between a multilayer wiring substrate made of an organic material, which is inexpensive and has a high linear expansion coefficient, and a semiconductor chip. By arranging the under-fill resin between the semiconductor chip and the multilayer wiring substrate made of an organic material, it is possible to disperse a shearing force exerted on a bump connection portion existing between the semiconductor chip and the multilayer wiring substrate made of an organic material and to thereby enhance mounting reliability. In this way, it is possible to employ a multilayer wiring substrate made of an inexpensive organic material by interposing an under-fill resin between the semiconductor chip and the multilayer wiring substrate made of the organic material.
Nevertheless, with this conventional technique, if voids exist in the under-fill resin, or the bonding characteristic at the interface between the under-fill resin and the semiconductor chip and the interface between the under-fill resin and the multilayer wiring substrate made of an organic material are not good, a separation of the bonding portion occurs at the interfaces in a step of reflow absorbing the moisture to a product to thereby disadvantageously make the product defective. For that reason, the above-stated conventional technique does not ensure reducing the cost of a flip chip type semiconductor device.
Further, a multilayer wiring substrate referred to as a buildup substrate is normally employed for a multilayer wiring substrate made of an organic material for a flip chip type semiconductor device because of the shortest pitch of a bump array pattern and the number of pins. A method of manufacturing this buildup substrate will be described with reference to FIGS. 2A to 2F.
First, as shown in FIG. 2A, a Cu foil layer 111 having a predetermined thickness of 10 to 40 xcexcm is bonded to each surface of a core substrate 110 made of an insulating glass epoxy material and patterning is conducted to the Cu foil layer 111. After forming holes in the core substrate 110 by drilling or the like, the through holes are subjected to a plating processing, thereby forming penetrating through hole sections 112 to electrically connect the Cu foil layers 111 on the both surfaces of the core substrate 110 to each other. In that case, an insulating resin layer 113 is usually filled in the penetrating through hole section 112 in light of the process stability of later steps and the quality stability of the substrate.
Next, as shown in FIG. 2B, an insulating resin layer 114 is arranged on the Cu wiring pattern existing on the front and rear surfaces of the core substrate 110, respectively and openings 115 are thereby formed at predetermined positions of the insulating resin layer 114 by a chemical etching method utilizing a photoresist technique, a laser processing technique or the like.
Then, as shown in FIG. 2C, metal thin layers 16 are formed by sputtering metal such as Ti or Cu, or by electroless plating Cu on the insulating resin layer 114 so as to secure the electrical connection between a feed layer for electrolytic plating of Cu and the Cu wiring pattern on the core substrate.
Thereafter, as shown in FIG. 2D, to form a wiring pattern by electrolytic plating of Cu, a photo-resist 117 or a dry film having a thickness of about 20 to 40 xcexcm is arranged on each surface of the metal thin film layer 116, and exposure and development processing is conducted thereto.
As shown in FIG. 2E, using the exposed metal thin film layers 116 as feed layers, an electrolytic plating of Cu is conducted to thereby form wiring pattern sections 118.
Then, as shown in FIG. 2F, after separating the photoresists 117 or dry films, using the wiring pattern sections 118 as a mask, the metal thin film layers 116 are removed by wet etching and the wiring pattern sections 118 are made electrically independent.
By repeating the steps shown in FIGS. 2B to 2F, it is possible to form a multilayer wiring substrate having six or eight metal layers according to necessity.
However, in the above-stated buildup substrate manufacturing method, it is necessary to employ photoresists 117 or dry films each having a thickness of about 20 to 40 xcexcm so as to secure the thickness of the buildup layer wiring pattern sections in view of the relax of a stress caused by the difference in the thermal expansion coefficient between the core substrate 110 and the buildup substrate and the reliability of the multilayer wiring substrate such as the reliability of connection via hole sections and the like. Due to this, it is necessary to use photoresists 117 or dry films each having a thickness of 20 to 40 xcexcm. Pattern formation characteristic which can be realized, is only about 30 xcexcm at the shortest pitch in exposure and development steps accordingly. As a result, the wiring pattern pitch becomes 30 xcexcm at the shortest and it is impossible to promote making the multilayer wiring substrate high in density and the outer shape of the substrate small in size. Further, an ordinary buildup substrate manufacturing method adopts manufacturing steps of creating products altogether on a large panel of about 500 mmxc3x97600 mm and cutting the panel in a final step to thereby take out a plurality of multilayer wiring substrates. Due to this, if it is possible to make the outer dimension of a single multilayer wiring substrate small, the number of multilayer wiring substrates per panel can be increased. According to the conventional buildup substrate manufacturing method, however, the wiring pattern pitch described above can be shortened to a minimum of about 30 xcexcm. It is, therefore, impossible to shorten the outer dimension of a single multilayer wiring substrate and difficult to greatly reduce multilayer wiring substrate cost.
The above-stated multilayer wiring substrate manufacturing method is also encountered by a warpage problem. Namely, the core substrate 110 warps. In exposure and development steps for forming buildup wiring patterns, the misalignment of resist patterns occurs due to the warp of the core substrate 110. This misalignment causes the deterioration of manufacturing yield.
Moreover, it is necessary to form buildup layers on the front and rear surfaces of the core substrate 110, respectively, which are not essentially required, so as to suppress the core substrate 110 from warping. As a result, an organic multilayer wiring substrate is forced to include more layers than necessary, which deteriorates manufacturing yield and thereby hampers the reduction of manufacturing cost.
As means for solving the above-stated disadvantages, the inventors of the present application proposed a technique disclosed in Japanese Patent Application No. 11-284566(filed in the Japanese Patent Office on 1999). According to this prior application, there is provided a constitution in which a buildup wiring layer serving as the second substrate layer is formed on the first substrate (Base substrate) having flatness and high rigidity. It is noted that this prior application is not published for public inspection at the time of filing the present application and it does not, therefore, become a prior art.
Then, the first substrate (Base substrate) having flatness and high rigidity is selectively etched away to thereby form external electrode column sections. After forming an insulating stress buffer resin layer around each external electrode column section, a solder ball is formed as an external terminal.
By this constitution, wiring layers or, in particular, multilayer wirings which are dynamically restricted by either a material or a base layer capable of maintaining high flatness are formed. As a result, the occurrence of an internal stress to the multilayer wiring layer is suppressed, thereby making it possible to enhance yield in semiconductor device manufacturing steps.
Furthermore, the solder ball sections used to be mounted on a substrate by an end user""s side are formed on the external electrode column sections surrounded by the insulating stress buffer resin layer. Due to this, it is possible to increase the standoff height of each solder ball. Besides, since the stress buffer effect of the insulating stress buffer resin layer is added, a flip chip type semiconductor device excellent in mounting reliability can be obtained.
Moreover, it is not always necessary to form a metal thin film wiring thick of about 10 to 30 xcexcm unlike a buildup substrate according to the conventional technique and a semiconductor wafer metalization manufacturing method and a manufacturing apparatus therefor can be utilized. Thus, it is possible to easily process the thickness of each photoresist and that of a metal thin film wiring section in a region as thin as 1 xcexcm or less and to easily form a smaller-sized wiring pattern. Additionally, by making the wiring pattern smaller in size, it is possible to increase the density of the organic multilayer wiring substrate, to decrease the outside dimensions of a single multilayer wiring substrate and to thereby considerably reduce cost.
Further, each package can be manufactured by a wafer level processing, so that the number of steps can be advantageously, greatly reduced compared with a packaging method for manufacturing packages from a single piece and cost can be advantageously, considerably reduced.
Nevertheless, with the structure proposed by Japanese Patent Application No. 11-284566, in a step of selectively etching away the first substrate (Base substrate) layer having flatness and high rigidity to thereby form external electrode column sections, if the thickness of the first substrate (Base substrate) is quite large at least 1.0 mm, the etching-away step for forming the external electrode column sections is disadvantageously made quite difficult to execute accordingly.
To execute the etching-away step, there are two methods, i.e., a wet etching method and a dry etching method. In case of the wet etching method using chemicals, the first substrate is etched isotropically, i.e., etching is conducted simultaneously in a thickness direction and a lateral direction. Due to this, if the thickness of the first substrate (Base substrate) is quite large at least 1.0 mm, in particular, it is difficult to ensure the stability of the shapes of the external electrode column sections, to minimize the irregularity of the shapes thereof, and to ensure product quality.
On the other hand, according to the dry etching method utilizing a plasma technique, the first substrate is etched anisotropically, i.e., etching is conducted in a thickness direction. This facilitates ensuring the stability of the shapes of the external electrode column sections and suppressing the irregularity of the shapes thereof. However, the normal etching rate of the dry etching method is as slow as 10 nm/minute to 100 xc3x85/minute. If the thickness of the first substrate (Base substrate) is as large as at least 1.0 mm, it takes longer to complete etching, which makes manufacturing time longer to thereby cause cost increase.
It is an object of the present invention to provide a flip chip type semiconductor device and a method for manufacturing the same capable of manufacturing a multilayer wiring substrate having a fine wiring pattern pitch of less than 10 xcexcm or low at low cost, preventing the occurrence of misalignment in a photolithographic step due to warpage of the substrate and avoiding disadvantages of longer etching time and longer manufacturing time.
A flip chip type semiconductor device according to the present invention comprises a multilayer wiring layer having a multilayer wiring structure; a substrate consisting of one of an insulating substrate and a multilayer wiring substrate having penetrating holes embedded with a conductive material; a bonding agent film interposed between the multilayer wiring layer and said substrate, and bonding the multilayer wiring layer to said substrate; and a semiconductor chip mounted on said multilayer wiring layer.
In this flip chip type semiconductor device, for example, the conductive material is a conductive bonding agent. And terminal balls may be coupled to the conductive bonding agent on a surface of the substrate. Also, for example, the flip chip type semiconductor device has an external electrode pad formed on an uppermost layer of the multilayer wiring layer; and a bump electrode provided on the semiconductor chip and connected to the external electrode pad.
Further, the flip chip type semiconductor device according the present invention may comprise an insulating resin layer for embedding side of the semiconductor chip; and a radiating heat spreader coupled to the semiconductor chip. Alternatively, the flip chip type semiconductor device according to the present invention may comprise a radiating heat spreader coupled to the semiconductor chip; and a stiffener arranged on each side of the semiconductor chip and interposed between the heat spreader and the multilayer wiring layer.
Meanwhile, a flip chip type semiconductor device manufacturing method according to the present invention comprises the steps of: forming a multilayer wiring structure on a first substrate consisting of a flat metal plate; etching away the first substrate to form a second substrate consisting of a multilayer wiring layer; coupling a third substrate to the second substrate consisting of the multilayer wiring layer to obtain a multilayer wiring substrate; and mounting a semiconductor chip on the second substrate.
In this flip chip type semiconductor device manufacturing method, the third substrate can be one of an insulating substrate and a multilayer substrate provided with holes.
Further, the second substrate can be manufactured by the steps of: forming an external electrode pad on the first substrate; forming an insulating thin film layer on an entire surface of the external electrode pad, and etching away the insulating thin film on the external electrode pad to form an opening; forming a metal thin layer on an entire surface, and patterning a resultant substrate to form a metal thin film wiring section connected to the external electrode pad in the opening; repeating formation of the insulating thin film layer and formation of the metal thin film wiring section; and forming an insulating resin thin film layer on an entire surface, forming an opening on the metal thin film wiring section below the insulating resin thin film layer and forming a pad electrode in the opening.
Moreover, it is possible to provide the step of embedding a conductive bonding agent into the hole of the third substrate and the step of coupling a solder ball onto the conductive bonding agent.
The semiconductor chip has a bump electrode; and in a step of mounting the semiconductor chip, the bump electrode is coupled to the external electrode pad of the second substrate.
Moreover, it is possible to provide the step of coupling a radiator to a reverse surface of the semiconductor chip through a heat transfer bonding agent. In this case, there are provided the steps of: coupling a stiffener on the second substrate at a position putting the semiconductor chip between the stiffener and the second substrate; and mounting the radiator on the semiconductor chip and the stiffener. Thus, it is possible to constitute a flip chip type semiconductor device to obtain the flatness of the multilayer wiring substrate.
According to the present invention, it is possible to maintain high flatness in the multilayer wiring substrate manufacturing steps, and to suppress the occurrence of an internal stress to the multilayer wiring layer. Further, after bonding the insulating substrate to this multilayer wiring layer, the semiconductor chip is mounted. Thus, semiconductor devices can be manufactured with high yield. Further, it is possible to employ an insulating substrate made of a material having a similar linear expansion coefficient as that of a mounting substrate employed by an end user side, on the lower layer of the multilayer wiring layer. In addition, since the solder ball is formed on the conductive bonding agent filled into the through hole in the insulating substrate, it is possible to facilitate enhancing a standoff height during mounting easily. Besides, since it is possible to minimize mismatch in the linear expansion coefficient, a flip chip type semiconductor device excellent in mounting reliability can be easily manufactured.
Furthermore, according to the present invention, it is not necessary to form the metal thin film wiring section thick or about 10 to 30 xcexcm unlike the conventional case, and a semiconductor wafer metalization manufacturing method and a manufacturing apparatus therefor can be utilized. Due to this, the thickness of a photoresist and that of the metal thin film wiring section can be processed in a thin range of 1 xcexcm or less, so that a finer wiring pattern can be easily obtained. Besides, by promoting a finer wiring pattern, it is possible to increase the density of an organic multilayer wiring substrate, to reduce the outer dimension of the single multilayer wiring substrate and to thereby greatly reduce manufacturing cost.
Moreover, according to the present invention, the Base substrate having high flatness is entirely removed. Thus, it is not necessary to selectively etch away this substrate, thereby making the manufacturing process quite simple.
Additionally, according to the present invention, it is possible to manufacture each package by a wafer level processing. Thus, compared with a packaging method of manufacturing respective packages from individual pieces, it is possible to greatly reduce the number of steps and to thereby greatly reduce cost.